Sense amplifier is typically used to read out the state, e.g., “0” or “1”, of the memory cell in a memory array, for example, ROM. A ROM array contains probably millions of memory cells arranged in rows and columns, each one of the memory cells in a column has a source that could be connected to a column source line, and during the sense amplifier is reading a selected memory cell, the column source line connected to the selected memory cell could be connected to a reference voltage or grounded. The drain of each one of the memory cells in a column is connected to an individual bit line, also known as column drain line, and during the sense amplifier is reading the selected memory cell, the column drain line connected to the selected memory cell is connected to the input of the sense amplifier. The control gate of each one of the memory cells in a row is connected to a word line, and the word line connected to the selected memory cell is connected to a predetermined voltage in the reading process.
During the reading operation, the current flowing through the selected memory cell is compared with a reference current to determine the selected memory cell is programmed with a “0” or a “1”. The reference circuit is coupled to the input of a current sense amplifier whose output is coupled to one input of a differential amplifier. When reading the selected memory cell, the differential amplifier compares the output voltage of the sense amplifier with the output voltage of another current sense amplifier coupled to the selected memory cell. If the reference circuit comprises a memory cell that is substantially identical to the selected memory cell, then the balance of the current sense amplifier is usually necessary to be broke for a reference current to be between the current of the selected memory cell being programmed with “0” and the current of the selected memory cell being programmed with “1”.
Precision control of the control clocks in timing is one of the fators for high speed operation in a sense amplifier. Unfortunately, due to the different process corners, temperature and voltage variations, the control clocks lack of well tracking capability and lead the sense amplifier difficult to be improved for the speed thereof. Referring to for example U.S. Pat. No. 5,771,196 issued to Yang, the control circuit consists of three blocks including the address transition pulse (ATP) generator, the precharge signal (PCB) generator and the latch signal (LATB) generator. The ATP signal is used as the trigger source of the control clocks, such as the precharge signal PCB, the latch signal LATB and the enable signal SAB of the sense amplifier. The precharge signal PCB should be the slower one of the word line delay and the bit line pull-up delay. For a flat ROM, the word line delay is much longer than the bit line pull-up delay, and thus, the word line delay is usually used to control the precharge signal PCB, and the width of the latch signal LATB should be larger than that of the precharge signal PCB. Further, the timing between the precharge signal PCB and latch signal LATB should be properly selected to latch correct data, and it is related to the sense time that is directly proportional to the memory cell current. The latch signal LATB is produced by adding a delay to the precharge signal PCB, in which the delay is controlled by the memory cell current from the mini-array, and the precharge signal PCB raises after several nanoseconds after the latch signal LATB to for correct data to be latched. In prior arts, the control signals are generated by referring to the memory cell current of the mini-array use in combination with RC (i.e., word line) delay and gate delay. Nevertheless, due to the different process corners, temperature and voltage variations, the control clocks lack of well tracking capability and as a result, it is difficult to improve the speed of the sense amplifier.
Therefore, it is desired a scheme to generate control clocks for high speed sense amplifier.